Design of RNS frequency sampling filter banks

Uwe Meyer-B ase, Jon Mellott, and Fred Taylor University of Florida, High Speed Digital Architecture Laboratory 405 SE BLDG 42,Gainesville, FL 32611-6130 USA fuwe,jon,[email protected] .edu ABSTRACT Frequency sampling lters (FSF) are of interest to the designers of multirate lter banks due to their intrinsic loworder, complexity, and linear phase behavior. Fast FSFs residing in smaller packages will be required to support future high-bandwidth, mobile image and signal processing applications. Since FSF designs rely on the exact annihilation of selected poles-zeros, a new facilitating technology is required which is fast, compact, and numerically exact. Exact FSF pole-zero annihilation is guaranteed by implementing polynomial lters over an integer ring in the residue arithmetic system (RNS). The design methodology is evaluated as an ASIC. Based on an FPGA technology, at least an 86% complexity reduction can be achieved with even greater advantages gained as a custom VLSI. An RNS-based FSF implementation of an eight channel cochlea lter bank is presented which demonstrates both the performance and packaging advantages of the new FSF paradigm. .